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<title><![CDATA[EC21 Product Catalogs - sram memory]]></title>
<link><![CDATA[https://www.ec21.com/ec-market/sram_memory--100103/1/sram memory.html]]></link><item>
<title><![CDATA[Dspic30f2010-i/Sp]]></title><link><![CDATA[https://semiraj1703.en.ec21.com/Dspic30f2010_i_Sp--12033594_12033595.html]]></link><description><![CDATA[The dsPIC30F2010 is a 16-bit digital signal controller (DSC) from Microchip Technology that has the following features:CPU speed: 120 MHz maximum, 30 MIPS/DMIPS Program memory: 12 KB SRAM: 0.5 KB Ope]]></description><pubDate><![CDATA[20241228]]></pubDate></item>
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<title><![CDATA[Original New Stm32f103c8t6 32-bit Microcontroller LQFP-48 IC Chip 64k Bom IC]]></title><link><![CDATA[https://oceanelectronic.en.ec21.com/Original_New_Stm32f103c8t6_32_bit--11963714_11982478.html]]></link><description><![CDATA[memories (up to 128 KB Flash and up to 20 KB SRAM), and a large number of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general-purpose 16-bit tim]]></description><pubDate><![CDATA[20240808]]></pubDate></item>
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<title><![CDATA[32-bit Low-cost General-purpose Microcontroller MCU 72MHz ARM Cortex-M0 64KB Flash Memory]]></title><link><![CDATA[https://zhangfei1electronics.en.ec21.com/32_bit_Low_cost_General--11875306_11877015.html]]></link><description><![CDATA[memory and 4KB SRAM.
The controller&apos;s peripherals include:
2 UART ports
1 I2C bus interface
1 SPI interface
4 timers/counters
1 6-channel PWM
1 watchdog timer (WDT)
1 high-speed 12-bit ADC
1 analog c]]></description><pubDate><![CDATA[20231222]]></pubDate></item>
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<title><![CDATA[Microcontroller Soc Cy8c27443 Microprocessor Psoc MCU Programmable System-on-Chip IC CYPRESS]]></title><link><![CDATA[https://band.en.ec21.com/Microcontroller_Soc_Cy8c27443_Microprocessor_Psoc--10880041_10880581.html]]></link><description><![CDATA[memory, SRAM data memory, and 
configurable I/O are included in a range of convenient pinouts 
and packages. 
The PSoC architecture, as illustrated in Logic Block Diagram on 
page 1, consists of four]]></description><pubDate><![CDATA[20181225]]></pubDate></item>
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<title><![CDATA[Hima Safety Systems B 5231]]></title><link><![CDATA[https://wendywen6666.en.ec21.com/Hima_Safety_Systems_B_5231--7823023_7823071.html]]></link><description><![CDATA[memory for the operating system and the user program usable for min. 100,000 writing cycles &amp;ndash; Data memory in sRAM &amp;ndash; Multiplexer to connect I/O bus, DPR and redundant CU (not used in the H]]></description><pubDate><![CDATA[20130411]]></pubDate></item>

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