Min. Order:
15 Piece
Price:
US$ 3
Place of origin:
Thailand
Modified Harvard architecture, C compiler optimized instruction set architecture Instructions: 24-bit wide instructions, 16-bit wide data path DSP engine: Modulo and Bit-Reversed modes, 17-bit x 17-bit single-cycle hardware fractional/integer multiplier, 40-stage Barrel Shifter, Dual data fetch Peripheral features: High current sink/source I/O pins, 3 16-bit timers/counters, 4 16-bit capture inpu
[Related Keywords : MICROCHIP, INTEGRATED CIRCUITS]